Physical Design Manager

Normal Computing

. Lead the physical design team, including hiring, individual guidance, and performance feedback .

Posted 10/16/2026full-timeMountain View • California • United StatesSeniorLead💰 $200,000 - $400,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in leading physical design teams and managing the complete tapeout process from netlist to signoff, with a strong focus on timing closure and physical design methodologies. Proficient in utilizing industry-standard EDA tools and collaborating effectively with cross-functional teams to optimize power, performance, and area.

Highest-signal resume keywords

Tapeout ManagementPhysical Design ToolsSTA Timing ClosureFloorplanningP&R Implementation

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Tapeout ManagementFloorplanningPlace-and-Route (P&R)Clock Tree Synthesis (CTS)Signoff Timing ClosurePower Integrity AnalysisIR/EM AnalysisCrosstalk AnalysisDRC ChecksLVS Checks

Soft Skills

Problem-SolvingCollaborationLeadership

Tools & Technologies

InnovusIC Compiler IITempusPrimeTimePegasusCalibreTCL ScriptingPython Scripting

Industry Keywords

Physical DesignEDA ToolsHigh-Performance ComputingAI Chip DesignCustom Memory Floorplanning

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Lead the physical design team, including hiring, individual guidance, and performance feedback
Create work estimates and schedules supporting an aggressive tapeout plan
Specify and help negotiate appropriate EDA tools for the physical design methodology
Collaborate with RTL, architecture, and DFT teams on early floorplanning, macro placement, pin assignments, and physical feasibility
Lead the netlist-to-GDSII physical design flow, including floorplanning, power grid design, placement, CTS, and P&R
Own STA, timing constraint creation and validation, and signoff timing closure across operating corners and modes
Drive PPA optimization, power integrity analysis, IR/EM analysis, and crosstalk analysis
Execute chip/block physical signoff checks, including DRC, LVS, ERC, and antenna fixes
Create and execute tapeout checklists and manage final stream-out processes
Support post-silicon physical debugging and bring-up as needed

Requirements

What you’ll need

Lead at least 3+ successful tapeouts from netlist to signoff, ideally across advanced technology nodes
Deep hands-on experience with industry-standard physical design tools, including Innovus, IC Compiler II, Tempus, PrimeTime, Pegasus, or Calibre
Experience across floorplanning, place-and-route (P&R), clock tree synthesis (CTS), and signoff timing closure
Strong problem-solving skills analyzing and resolving STA timing bottlenecks, IR/EM drop issues, crosstalk, and complex DRC/LVS signoff violations
Ability to collaborate with RTL, architecture, and DFT teams on floorplanning, pin placement, and early physical feasibility
At least 7 years of experience in the role
Experience at an AI or high-performance computing chip startup is a bonus
Experience with custom memory/macro floorplanning, hierarchical top-level implementation, or advanced packaging is a bonus
Hands-on experience developing or maintaining automated TCL/Python scripting frameworks is a bonus

Benefits

Comp & perks

Equity
Competitive and equitable compensation
Reasonable accommodations for individuals with disabilities