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OpenAI

Silicon Design Lead

OpenAI

. Own architecture, microarchitecture, and implementation of silicon IP and subsystems from requirements and design specifications through integration and validation .

Posted 11/4/2026full-timeSan Francisco • California • United StatesSenior💰 $287,000 - $485,000 per yearWebsite

Core Competencies

Role fit
Core Competencies

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Demonstrates expertise in silicon IP architecture and implementation, with a strong focus on hardware security mechanisms and the ability to translate functional and security requirements into effective hardware designs. Proficient in collaborating across teams to ensure successful subsystem integration and validation.

Highest-signal resume keywords
Silicon IP ArchitectureHardware Security FeaturesRTL DesignVerilog or SystemVerilog Coding ProficiencySubsystem Integration

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills
Silicon IPMicroarchitectureImplementationHardware InterfacesData FlowsMemory EncryptionKey ManagementAccess ControlsIsolationSecure Boot
Soft Skills
CollaborationEvaluationProblem-Solving
Industry Keywords
SoC-Level ArchitectureIntegrationSecurity ArchitectureThreat ModelsPerformance TradeoffsPower TradeoffsArea TradeoffsComplexity TradeoffsU.S. Export Control LawsVerification

About the role

Key responsibilities & impact
  • Own architecture, microarchitecture, and implementation of silicon IP and subsystems from requirements and design specifications through integration and validation
  • Define hardware interfaces, data flows, and microarchitectural tradeoffs to meet functional, performance, power, and area requirements
  • Partner with OpenAI’s Security team to translate security architecture, requirements, and threat models into implementable hardware capabilities
  • Design and integrate hardware security mechanisms, including encryption, key management, access controls, isolation, and data protection across silicon subsystems
  • Evaluate architectural and implementation tradeoffs to ensure security capabilities meet functional and performance requirements
  • Collaborate with silicon architects, RTL, verification, firmware, and software teams to drive subsystem design, integration, and validation
  • Review and contribute to RTL implementations, ensuring designs align with architectural intent and system requirements
  • Evaluate existing and third-party IP, identify architectural or implementation gaps, and drive solutions across subsystem boundaries

Requirements

What you’ll need
  • Strong experience in silicon IP or subsystem-level architecture, microarchitecture, and implementation
  • Experience owning hardware IP or subsystem designs from architectural definition through implementation and integration
  • Experience implementing hardware security features such as memory encryption, key management, access controls, isolation, or secure boot
  • Understanding of translating functional and security requirements into hardware architectures, interfaces, and microarchitectural specifications
  • Working knowledge of RTL design
  • Coding proficiency in Verilog or SystemVerilog
  • Ability to read, review, and contribute to RTL
  • Ability to evaluate performance, power, area, and complexity tradeoffs across silicon designs
  • Ability to work across security, silicon architecture, RTL, verification, firmware, and software teams
  • Broader SoC-level architecture or integration experience is ideally preferred, though deep IP or subsystem-level expertise is sufficient
  • May need to meet certain legal status requirements under U.S. export control laws and regulations

Benefits

Comp & perks
  • Equity
  • Performance-related bonuses for eligible employees
  • Medical, dental, and vision insurance for you and your family
  • Employer contributions to Health Savings Accounts
  • Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)
  • 401(k) retirement plan with employer match
  • Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents)
  • Paid medical and caregiver leave (up to 8 weeks)
  • Flexible PTO for exempt employees and up to 15 days annually for non-exempt employees
  • 13+ paid company holidays
  • Multiple paid coordinated company office closures throughout the year
  • Paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)
  • Mental health and wellness support
  • Employer-paid basic life and disability coverage
  • Annual learning and development stipend
  • Daily meals in offices
  • Meal delivery credits as eligible
  • Relocation support for eligible employees
  • Charitable donation matching and wellness stipends may also be provided