Apply

Ready to go for it?

AI Apply speeds things up—apply directly if you prefer.

FREE ACCESS
5,000–10,000 jobs/day
Scoutfield Logo

See all jobs on Scoutfield

Search thousands of fresh jobs every day.

Discover
  • Fresh listings
  • Fast filters
  • No subscription required
Create a free account and start exploring right away.
OpenAI

SoC Engineer

OpenAI

. Architect, design, and integrate OpenAI’s first-party AI accelerators .

Posted 10/14/2026full-timeSan Francisco • California • United StatesMid-LevelSenior💰 $287,000 - $485,000 per yearWebsite

Core Competencies

Role fit
Core Competencies

Use this summary to align your resume positioning with the role.

Demonstrates expertise in SoC architecture, RTL design, and integration of embedded processors, with a strong focus on high-speed I/O and security requirements. Proficient in collaborating with cross-functional teams to drive successful silicon bring-up and validation.

Highest-signal resume keywords
SoC ArchitectureRTL DesignArm Cortex-M and Cortex-A IntegrationPCIe ProtocolsDebug and Security Design

ATS Keywords

Tailor your resume
Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills
SoC ArchitectureRTL DesignVerilog/SystemVerilogHigh-Speed I/O IntegrationDebug and Test DesignPower ManagementBoot ArchitectureAutomation Tools DevelopmentFirmware and Software InteractionIntegration with Third-Party IP
Tools & Technologies
AMBA ProtocolsAXI InterconnectAPB InterconnectSerDes InterfacesPHY Interfaces
Industry Keywords
Silicon Bring-UpPre-Silicon ValidationPost-Silicon Bring-UpIntegration Issues ResolutionU.S. Export Control Laws

About the role

Key responsibilities & impact
  • Architect, design, and integrate OpenAI’s first-party AI accelerators
  • Build processor, interconnect, I/O, and platform infrastructure connecting accelerator designs into complete systems
  • Define and implement SoC architectures spanning embedded processors, AMBA interconnects, peripheral subsystems, PCI Express, Ethernet, and die-to-die interfaces
  • Develop microarchitecture and RTL for I/O and SoC subsystems
  • Integrate Arm Cortex-M and Cortex-A processors, AXI/APB fabrics, and third-party controller IP
  • Develop reset and boot architectures with firmware and software teams
  • Incorporate debug, test, and security requirements into SoC architecture and implementation
  • Drive PCIe and other I/O integration, including controller and PHY interfaces, high-speed SerDes, and die-to-die connectivity
  • Contribute to power management and security architecture and design
  • Work with third-party IP vendors to define requirements, evaluate capabilities, coordinate deliverables, and resolve integration issues through silicon bring-up
  • Collaborate across architecture, design, verification, physical design, and software teams
  • Carry designs through pre-silicon validation and post-silicon bring-up
  • Define boot, configuration, runtime behavior, and functionality with Firmware and Software teams
  • Build and apply automation and AI-assisted tools for design, IP integration, consistency checking, and debugging

Requirements

What you’ll need
  • Experience in SoC architecture, RTL design, and subsystem or full-chip integration, with hands-on ownership through implementation and silicon bring-up
  • Familiarity with Arm processor subsystems, including Cortex-M and Cortex-A
  • Familiarity with AMBA protocols and interconnects such as AXI and APB
  • Understanding of PCIe protocols and experience configuring, integrating, and debugging controller IP
  • Experience integrating high-speed I/O, including SerDes/PHY interfaces and die-to-die links
  • Experience working directly with third-party IP vendors to evaluate technical fit, communicate requirements, and resolve integration and debug issues
  • Understanding of reset and boot architecture and hardware, firmware, and software interactions during initialization and recovery
  • Experience designing for debug, test, and security
  • Ability to write and debug Verilog/SystemVerilog
  • Ability to build scripts or tools for efficient and reliable integration work
  • Candidates may need to meet certain legal status requirements under U.S. export control laws and regulations
  • Ability to work from the US office three days per week

Benefits

Comp & perks
  • Equity
  • Performance-related bonus(es) for eligible employees
  • Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts
  • Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)
  • 401(k) retirement plan with employer match
  • Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents)
  • Paid medical and caregiver leave (up to 8 weeks)
  • Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees
  • 13+ paid company holidays
  • Multiple paid coordinated company office closures throughout the year for focus and recharge
  • Paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)
  • Mental health and wellness support
  • Employer-paid basic life and disability coverage
  • Annual learning and development stipend
  • Daily meals in offices
  • Meal delivery credits as eligible
  • Relocation support for eligible employees
  • Additional taxable fringe benefits, such as charitable donation matching and wellness stipends, may also be provided.