Senior/Staff Design Verification Engineer

Powerlattice Inc

. Lead verification planning and execution for complex digital and mixed-signal subsystems .

Posted 9/23/2026full-timeUnited StatesSenior💰 $160,000 - $190,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in digital verification of SoCs, including the development of SystemVerilog-based verification environments and protocol-based test infrastructure. Proficient in constrained-random verification, regression automation, and collaboration with cross-functional teams to ensure comprehensive verification coverage.

Highest-signal resume keywords

Digital Verification of SoCsSystemVerilog-Based VerificationUVM and Class-Based Verification MethodologiesConstrained-Random VerificationEDA Tools (Synopsys, Cadence)

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

SystemVerilogVerilogUVMPythonPerlUNIX/Linux Shell ScriptingVerification IP DevelopmentRegression AutomationFormal Verification TechniquesDigital Design Fundamentals

Soft Skills

Analytical SkillsProblem-Solving SkillsCommunication SkillsMentorshipTechnical Leadership

Tools & Technologies

XceliumVCSEDA Tools (Synopsys, Cadence)

Industry Keywords

I2CI3CSPIJTAGOBICDCRDCMixed-Signal SubsystemsSoC IntegrationPMIC Architectures

Tech Stack

Tools & technologies

LinuxPerlPythonShell ScriptingUnix

About the role

Key responsibilities & impact

Lead verification planning and execution for complex digital and mixed-signal subsystems
Define verification strategies, test scenarios, coverage goals, and signoff criteria
Architect, develop, and maintain SystemVerilog-based verification environments and reusable infrastructure
Develop directed, constrained-random, regression, and corner-case tests
Develop reusable verification components and protocol-based test infrastructure for I2C/I3C, SPI, JTAG, AMBA, and OBI interfaces
Perform and support CDC verification for asynchronous and synchronous clock-domain interfaces
Develop and maintain UVM-based infrastructure and RAL models
Develop checkers, scoreboards, reference models, assertions, and functional coverage
Perform RTL and gate-level simulation, including SDF-annotated GLS
Develop and optimize regression and GLS flows using Xcelium and VCS
Analyze functional and code coverage and drive coverage closure
Debug RTL, testbench, simulation, and gate-level failures using waveform and log analysis
Collaborate with RTL designers, analog designers, architects, and silicon validation teams to resolve issues
Review specifications and RTL for corner cases, interface issues, reset/clocking problems, and functional gaps
Translate silicon validation findings into simulation-based verification scenarios and regression tests
Provide technical leadership and mentorship to verification engineers

Requirements

What you’ll need

Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field
10+ years of experience in digital verification of SoCs with proven ownership of subsystems or full-chip verification
Solid understanding of digital design fundamentals, FSMs, CDC, RDC, mixed-signal subsystems, and SoC integration
Knowledge of AMBA, I²C, I3C, SPI, JTAG, and OBI protocols
Expertise in Verilog, SystemVerilog, UVM, and class-based verification methodologies
Expertise in constrained-random, coverage-driven verification, regression automation, and verification signoff
Expertise in SystemVerilog Assertions (SVA) and formal verification techniques
Proficiency in Python, Perl, and UNIX/Linux shell scripting for automation
Hands-on experience developing testbenches, drivers, monitors, scoreboards, assertions, and reusable verification IP
Experience with industry-standard EDA tools (Synopsys, Cadence)
Strong analytical and problem-solving skills; ability to debug complex issues, communicate clearly, mentor engineers, lead technical initiatives, and collaborate cross-functionally
Preferred: working knowledge of PMIC architectures and power management principles
Preferred: experience with formal verification techniques
Legally authorized to work in the United States

Benefits

Comp & perks

Stock option grant
Comprehensive benefits package including health, dental, vision, and 401(k)