Powerlattice Inc

Designer

• Lead verification planning and execution for complex digital and mixed-signal subsystems
• Define verification strategies, test scenarios, coverage goals, and signoff criteria
• Architect, develop, and maintain SystemVerilog-based verification environments and reusable infrastructure
• Develop directed, constrained-random, regression, and corner-case tests
• Develop reusable verification components and protocol-based test infrastructure for I2C/I3C, SPI, JTAG, AMBA, and OBI interfaces
• Perform and support CDC verification for asynchronous and synchronous clock-domain interfaces
• Develop and maintain UVM-based infrastructure and RAL models
• Develop checkers, scoreboards, reference models, assertions, and functional coverage
• Perform RTL and gate-level simulation, including SDF-annotated GLS
• Develop and optimize regression and GLS flows using Xcelium and VCS
• Analyze functional and code coverage and drive coverage closure
• Debug RTL, testbench, simulation, and gate-level failures using waveform and log analysis
• Collaborate with RTL designers, analog designers, architects, and silicon validation teams to resolve issues
• Review specifications and RTL for corner cases, interface issues, reset/clocking problems, and functional gaps
• Translate silicon validation findings into simulation-based verification scenarios and regression tests
• Provide technical leadership and mentorship to verification engineers

Senior/Staff Design Verification Engineer