Debug and Trace Architect

RosaicLabs Inc

. Own the SoC debug and trace specification, including run-control access, a common trace record format, and observability requirements for bring-up, performance diagnosis, and failure analysis .

Posted 11/11/2026full-timeUnited StatesSeniorLead💰 $250,000 - $300,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Expertise in SoC and ASIC architecture with a strong focus on debug, trace, and performance-monitoring features. Proven ability to define specifications, coordinate cross-functional teams, and drive silicon validation processes.

Highest-signal resume keywords

SoC ArchitectureDebug SpecificationTrace CapturePerformance MonitoringSilicon Validation

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

JTAGRun ControlPerformance CountersDebug Data InterpretationMicroarchitecture DesignTrace Funnel ArchitectureCross-Die SynchronizationTechnical Specification WritingSilicon Bring-UpHigh-Bandwidth Trace Collection

Tools & Technologies

PCIeFirmware ControlDebug Logic

Industry Keywords

Electrical EngineeringComputer EngineeringComputer ScienceSilicon ValidationASIC DesignPerformance DiagnosisFailure AnalysisObservability Requirements

About the role

Key responsibilities & impact

Own the SoC debug and trace specification, including run-control access, a common trace record format, and observability requirements for bring-up, performance diagnosis, and failure analysis
Define secure JTAG and run-control behavior for compute engines, cores, management controllers, and other relevant subsystems, including halt and step capabilities
Specify instruction, compute-engine, microcontroller, fabric-transaction, die-to-die, and network-gateway trace sources
Architect trace funnels, cross-die triggers, on-chip buffers, and a synchronized package-wide time base aligned with RAS error records
Define trace capture and export paths, including optional spill to memory and readout over PCIe; set bandwidth limits and measure tracing's effect on workloads
Architect performance-monitoring units and counters exposing stalls, latency, contention, and other behavior needed by software and silicon teams
Define post-mortem capture and crash-dump requirements, including what remains accessible after a subsystem fault or host-link reset
Establish authenticated debug-unlock levels with the Security Architect so production debug cannot expose protected data or secrets
Set validation criteria for run control, counters, trace records, decoders, and performance tools
Coordinate firmware control, silicon bring-up, and software export formats

Requirements

What you’ll need

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience
At least 12 years of experience in SoC or ASIC architecture, design, verification, or silicon validation
At least 3 years defining or leading debug, trace, performance-monitoring, or silicon-observability features
Experience taking a debug or observability feature from specification through design and verification to silicon bring-up or production use
Working knowledge of run control, JTAG, trace capture, performance counters, and hardware and software interfaces for collecting and interpreting debug data
Experience writing technical specifications and resolving implementation tradeoffs with RTL, verification, firmware, software, and silicon validation teams
Experience synchronizing trace across multiple dies or subsystems, including timestamp alignment and cross-triggering
Familiarity with high-bandwidth trace collection, memory-backed capture, PCIe export, or tools that convert hardware traces into software-readable formats
Ability to drive the microarchitecture of trace funnels, counters, capture buffers, triggers, and related debug logic

Benefits

Comp & perks

Medical (including HSA plans)
Dental
Vision
Employee Life & AD&D insurance
401(k)