RosaicLabs Inc

Engineer

• Define and evaluate silicon power-management features, including clock gating, power gating, idle states, and dynamic voltage and frequency scaling.
• Specify expected power savings, performance impact, and conditions for entering and exiting power-management states.
• Develop representative, high-activity, and corner-case workloads for power measurement in simulation, emulation, and silicon.
• Collaborate with verification and software teams to make workloads reproducible and representative of intended use.
• Establish power targets for IP blocks and dies.
• Produce power rollups across workloads, operating points, and design revisions, including dynamic and leakage power where appropriate.
• Run and interpret RTL and gate-level power analysis.
• Use switching activity, power reports, and design data to identify major contributors, unexpected activity, and gaps against targets.
• Partner with RTL teams to evaluate clock enables, operand isolation, reduced data movement, and low-power states.
• Partner with physical design teams to assess the power impact of synthesis, clock distribution, placement, and implementation choices while balancing timing, area, and performance.
• Build and refine power models and analysis flows comparing architectural estimates with implementation results and measured silicon data when available.
• Track power optimizations through implementation and measurement, quantify savings, and document tradeoffs.
• Communicate power trends, risks, and recommendations to design and architecture teams throughout the silicon development cycle.

Explore Silicon Power Engineer at RosaicLabs Inc. Review requirements and application details.

Silicon Power Engineer

Architect

• Own the SoC debug and trace specification, including run-control access, a common trace record format, and observability requirements for bring-up, performance diagnosis, and failure analysis
• Define secure JTAG and run-control behavior for compute engines, cores, management controllers, and other relevant subsystems, including halt and step capabilities
• Specify instruction, compute-engine, microcontroller, fabric-transaction, die-to-die, and network-gateway trace sources
• Architect trace funnels, cross-die triggers, on-chip buffers, and a synchronized package-wide time base aligned with RAS error records
• Define trace capture and export paths, including optional spill to memory and readout over PCIe; set bandwidth limits and measure tracing's effect on workloads
• Architect performance-monitoring units and counters exposing stalls, latency, contention, and other behavior needed by software and silicon teams
• Define post-mortem capture and crash-dump requirements, including what remains accessible after a subsystem fault or host-link reset
• Establish authenticated debug-unlock levels with the Security Architect so production debug cannot expose protected data or secrets
• Set validation criteria for run control, counters, trace records, decoders, and performance tools
• Coordinate firmware control, silicon bring-up, and software export formats

Explore Debug and Trace Architect at RosaicLabs Inc. Review requirements and application details.

Debug and Trace Architect

• Define the system power architecture and allocate power budgets across compute chiplets, I/O dies, memory interfaces, high-speed links, and the package.
• Own the rail plan and voltage domains; specify current, transient, droop, sequencing, and monitoring requirements for each domain.
• Work with package and platform teams to evaluate board-level and in-package voltage regulation, regulator placement and control, rail entry, power distribution, and thermal constraints.
• Specify power-on, ramp, boot, reset, shutdown, idle-entry, and fault-recovery flows.
• Architect power-management control and communication across dies, including controller and agent responsibilities, control paths, and failure handling.
• Define DVFS, clock and power gating, package idle states, and memory low-power transitions.
• Define package power-cap enforcement, thermal throttling, fast response to droop or overcurrent, and limits on rapid current-draw changes.
• Specify host, BMC, operating-system, and firmware interfaces for power caps, performance controls, telemetry, and emergency responses.
• Develop activity-based power models and energy estimates to guide architectural tradeoffs and verify power budgets.
• Establish verification and validation requirements for power states, transitions, faults, and recovery, including power-aware simulation and UPF-based checks.
• Work closely with silicon, package, platform, firmware, and performance teams across architecture, implementation, and validation.

Explore Power Management Architect at RosaicLabs Inc. Review requirements and application details.

Open roles

Silicon Power Engineer

Debug and Trace Architect

Power Management Architect