Power Management Architect

RosaicLabs Inc

. Define the system power architecture and allocate power budgets across compute chiplets, I/O dies, memory interfaces, high-speed links, and the package.

Posted 11/11/2026full-timeUnited StatesSeniorLead💰 $250,000 - $300,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

Use this summary to align your resume positioning with the role.

Expertise in defining and architecting power management systems, including power budgets, voltage domains, and power-state sequencing. Proficient in activity-based power modeling and validation, collaborating with cross-functional teams to ensure effective implementation and verification.

Highest-signal resume keywords

SoC Power ArchitecturePower Delivery AnalysisRail Plan DefinitionDVFS ImplementationPower-Aware Simulation

ATS Keywords

Tailor your resume

Applicant Tracking System Keywords

Tip: use these terms in your resume and cover letter to boost ATS matches.

Hard Skills

Power Management ControlVoltage RegulationThermal ThrottlingChip Power BudgetsPower-State SequencingTransient Current AnalysisPower IntegrityMicroarchitecture of Power ControllersActivity-Based Power ModelingUPF-Based Checks

Certifications & Qualifications

Bachelor’s Degree in Electrical EngineeringBachelor’s Degree in Computer EngineeringBachelor’s Degree in Power Electronics

Industry Keywords

Multi-Domain Power ManagementHigh-Bandwidth MemoryLPDDR InterfacesHigh-Speed I/OPower CapsTelemetry LogicFault RecoveryCurrent Draw LimitsVoltage DomainsRegulator Requirements

About the role

Key responsibilities & impact

Define the system power architecture and allocate power budgets across compute chiplets, I/O dies, memory interfaces, high-speed links, and the package.
Own the rail plan and voltage domains; specify current, transient, droop, sequencing, and monitoring requirements for each domain.
Work with package and platform teams to evaluate board-level and in-package voltage regulation, regulator placement and control, rail entry, power distribution, and thermal constraints.
Specify power-on, ramp, boot, reset, shutdown, idle-entry, and fault-recovery flows.
Architect power-management control and communication across dies, including controller and agent responsibilities, control paths, and failure handling.
Define DVFS, clock and power gating, package idle states, and memory low-power transitions.
Define package power-cap enforcement, thermal throttling, fast response to droop or overcurrent, and limits on rapid current-draw changes.
Specify host, BMC, operating-system, and firmware interfaces for power caps, performance controls, telemetry, and emergency responses.
Develop activity-based power models and energy estimates to guide architectural tradeoffs and verify power budgets.
Establish verification and validation requirements for power states, transitions, faults, and recovery, including power-aware simulation and UPF-based checks.
Work closely with silicon, package, platform, firmware, and performance teams across architecture, implementation, and validation.

Requirements

What you’ll need

Bachelor’s degree in electrical engineering, computer engineering, power electronics, or a related field, or equivalent practical experience.
At least 12 years of relevant experience in SoC power architecture, power delivery, or complex multi-domain power-management design.
Direct experience defining rail plans, voltage domains, regulator requirements, and chip or package power budgets.
Experience architecting power-state sequencing, DVFS, power caps, and thermal or electrical throttling.
Experience carrying power-management requirements through implementation and verification in collaboration with silicon, package, platform, and firmware teams.
Power architecture for multi-die packages, high-bandwidth memory or LPDDR interfaces, and high-speed I/O.
Power-delivery analysis involving transient current, voltage droop, power integrity, and regulator tradeoffs.
Microarchitecture of power controllers, distributed agents, sequencers, or telemetry logic.
Activity-based power modeling, UPF, power-aware simulation, and silicon power validation.

Benefits

Comp & perks

Medical (including HSA plans)
Dental
Vision
Employee Life & AD&D
401(k)