RAS Architect

RosaicLabs Inc

. Own the end-to-end RAS specification, reliability and availability targets, FIT budget by domain, common error records and timestamps, and software-visible error-bank mapping where applicable .

Posted 11/11/2026full-timeUnited StatesSeniorLead💰 $250,000 - $300,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in RAS specification, reliability, and availability for SoC architecture, with a strong focus on error detection, correction, and recovery mechanisms. Proficient in translating complex RAS requirements into implementable designs and collaborating with cross-functional teams for silicon validation and production deployment.

Highest-signal resume keywords

SoC ArchitectureRAS Feature DefinitionError Detection and CorrectionSilent Data Corruption AnalysisFirmware-First Error Handling

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

ECCParityError LoggingFault InjectionPoison HandlingRecovery MechanismsSilicon ValidationDesign VerificationError Bank MappingTelemetry for Predictive Maintenance

Tools & Technologies

BMC IntegrationHigh-Speed LinksPCIeCXLHBMDDRLPDDR

Industry Keywords

Compute EnginesMemory ScrubbingIn-Field ScreeningGraceful DegradationMulti-Die Systems

About the role

Key responsibilities & impact

Own the end-to-end RAS specification, reliability and availability targets, FIT budget by domain, common error records and timestamps, and software-visible error-bank mapping where applicable
Define fault detection, correction, logging, and diagnosis across compute engines and cores, caches, HBM and LPDDR memory, die-to-die and scale-up links, PCIe/CXL, and management agents
Specify ECC, parity, residue checks, memory scrubbing, retirement or repair, and in-field screening to prevent and detect silent data corruption
Define end-to-end poison propagation, containment, retry, and recovery for correctable and uncorrectable errors, including failures that cross die or subsystem boundaries
Specify isolation, fencing, and degraded-operation behavior for compute units, cores or clusters, memory resources, links, and package-level failures
Define firmware-first error handling and reporting interfaces for drivers, the OS, BMC, and fleet management, including telemetry that supports predictive maintenance and field diagnosis
Translate RAS requirements into implementable interfaces for error banks, poison paths, injection hooks, logging, and recovery controls; review the resulting design and firmware behavior
Define per-domain error-injection hooks, verification coverage, and campaigns for cross-domain faults, containment, and recovery in simulation, emulation, and silicon
Work with DFT, reliability, verification, firmware, and software teams on in-field screening, silicon debug, and analysis of production and fleet failures

Requirements

What you’ll need

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience
At least 12 years of experience in SoC architecture, design, verification, silicon validation, or platform reliability, including at least 3 years defining or leading RAS features for a processor, accelerator, or server-class SoC
Experience carrying a RAS feature from architecture specification through design and verification to silicon bring-up or production deployment
Working knowledge of ECC or parity, error logging, poison handling, fault injection, containment, and recovery, including how hardware error behavior is exposed to firmware and software
Experience across at least two of these domains: compute and cache subsystems; HBM, DDR, or LPDDR memory; interconnects; or PCIe, CXL, and high-speed links
Familiarity with processor and uncore error-reporting architectures, firmware-first error handling, BMC integration, or fleet reliability telemetry
Experience with silent-data-corruption analysis, in-field screening, or graceful degradation of large multi-die systems
Ability to drive the microarchitecture of RAS logic blocks such as error banks, poison paths, injection controls, and recovery state machines
Required to verify identity and eligibility to work in the United States and complete the required employment eligibility verification form upon hire
Visa sponsorship is available for qualified candidates

Benefits

Comp & perks

Medical (including HSA plans)
Dental
Vision
Employee Life & AD&D
401(k)