Security Architect – Confidential Computing

RosaicLabs Inc

. Own the SoC threat model, security specification, trust boundaries, and key hierarchy across compute and I/O dies, memory, interconnects, host interfaces, and network links .

Posted 11/11/2026full-timeUnited StatesSeniorLead💰 $250,000 - $300,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in SoC architecture and hardware security, with a strong focus on defining security specifications, threat models, and root-of-trust architectures. Proven ability to coordinate cross-functional teams and drive the implementation of security features from design to production.

Highest-signal resume keywords

SoC ArchitectureSecurity SpecificationRoot Of TrustSecure BootMemory Protection

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Threat Model DefinitionFirmware MeasurementDevice AttestationMemory EncryptionDebug-Unlock LevelsMicroarchitecture DesignSecurity Validation CriteriaAccess Control ImplementationVerification Criteria DevelopmentSecurity Tradeoff Resolution

Soft Skills

Technical Specification WritingCross-Functional Coordination

Tools & Technologies

SPDMPCIe DOEMCTPDMA IsolationConfidential Computing

Industry Keywords

Hardware SecurityPlatform SecurityTrusted I/ODevice LifecycleSilicon Bring-Up

About the role

Key responsibilities & impact

Own the SoC threat model, security specification, trust boundaries, and key hierarchy across compute and I/O dies, memory, interconnects, host interfaces, and network links
Define the root-of-trust architecture, secure and measured boot, firmware measurement, fuse policy, and lifecycle states for platform, power-management, and dispatch firmware
Specify device, host, and trust-domain attestation, including SPDM, PCIe DOE, and MCTP interfaces
Architect confidential I/O and DMA isolation across PCIe and CXL, including IDE, TDISP, device-MMU and System-MMU ownership checks, and trust-domain integration
Define memory encryption and integrity requirements, including HBM protection, per-trust-domain keys, crypto-engine needs, and effects on memory throughput and migration
Define security boundaries for cross-die and network communication, including peer authentication, link protection, and key handling with interconnect and network architects
Set authenticated debug-unlock levels, secret-clearing rules, and authorization requirements for in-field test patterns
Establish security acceptance and validation criteria, including fault and glitch scenarios, isolation failures, and attestation flows
Coordinate implementation with RoT firmware, boot, memory, I/O, DFT, verification, and host software teams

Requirements

What you’ll need

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience
At least 12 years of experience in SoC architecture or design, hardware security, or platform security, including at least 3 years defining security architecture across hardware and firmware or software
Experience taking a hardware-rooted security feature from threat model and architecture specification through design and verification to silicon bring-up or production deployment
Practical experience in at least two of these areas: root of trust, secure boot and attestation; confidential computing and memory protection; trusted I/O and DMA isolation; or secure debug and device lifecycle
Experience writing technical specifications and resolving security tradeoffs with RTL, verification, firmware, and software teams
Ability to drive the microarchitecture of security-related logic blocks, translating system requirements into implementable interfaces, state machines, access controls, and verification criteria
Required to verify identity and eligibility to work in the United States and complete the required employment eligibility verification form upon hire

Benefits

Comp & perks

Visa sponsorship is available for this role for qualified candidates