Silicon Power Engineer

RosaicLabs Inc

. Define and evaluate silicon power-management features, including clock gating, power gating, idle states, and dynamic voltage and frequency scaling.

Posted 11/11/2026full-timeUnited StatesMid-LevelSenior💰 $125,000 - $250,000 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates expertise in silicon power management, including clock gating, power gating, and dynamic voltage and frequency scaling. Proficient in power analysis from RTL and gate-level designs, with strong collaboration skills to communicate findings and recommendations effectively.

Highest-signal resume keywords

Silicon Power OptimizationPower AnalysisVerilog or SystemVerilogPython ScriptingLow-Power Design

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Power Management FeaturesPower MeasurementRTL Power AnalysisDynamic Voltage and Frequency ScalingClock GatingPower GatingIdle StatesWorkload DevelopmentData AnalysisLeakage Power Analysis

Soft Skills

CollaborationCommunicationProblem-Solving

Tools & Technologies

Power Analysis ToolsAutomated Power RegressionsPhysical Design FlowsUPFClock Trees

Industry Keywords

ASIC DesignSoC DesignPower EstimationSilicon Development CycleDesign Improvements

Tech Stack

Tools & technologies

PythonSwitching

About the role

Key responsibilities & impact

Define and evaluate silicon power-management features, including clock gating, power gating, idle states, and dynamic voltage and frequency scaling.
Specify expected power savings, performance impact, and conditions for entering and exiting power-management states.
Develop representative, high-activity, and corner-case workloads for power measurement in simulation, emulation, and silicon.
Collaborate with verification and software teams to make workloads reproducible and representative of intended use.
Establish power targets for IP blocks and dies.
Produce power rollups across workloads, operating points, and design revisions, including dynamic and leakage power where appropriate.
Run and interpret RTL and gate-level power analysis.
Use switching activity, power reports, and design data to identify major contributors, unexpected activity, and gaps against targets.
Partner with RTL teams to evaluate clock enables, operand isolation, reduced data movement, and low-power states.
Partner with physical design teams to assess the power impact of synthesis, clock distribution, placement, and implementation choices while balancing timing, area, and performance.
Build and refine power models and analysis flows comparing architectural estimates with implementation results and measured silicon data when available.
Track power optimizations through implementation and measurement, quantify savings, and document tradeoffs.
Communicate power trends, risks, and recommendations to design and architecture teams throughout the silicon development cycle.

Requirements

What you’ll need

Bachelor’s degree in electrical engineering, computer engineering, or a related field, or equivalent practical experience.
At least 5 years of relevant experience in ASIC or SoC design, power analysis, low-power design, or silicon power optimization.
Hands-on experience analyzing power from RTL or gate-level designs and using the results to identify design improvements.
Working knowledge of Verilog or SystemVerilog, digital design, and the effects of switching activity, clocks, voltage, and leakage on power.
Experience developing or selecting workloads and activity traces for power estimation, and communicating results to design teams.
Proficiency with scripting or data analysis, preferably using Python.
Preferred: Experience defining and validating clock-gating, power-gating, idle-state, or DVFS features.
Preferred: Experience with industry-standard RTL or gate-level power analysis tools and automated power regressions.
Preferred: Experience correlating pre-silicon estimates with lab power measurements and investigating differences.
Preferred: Familiarity with physical design flows, clock trees, UPF, and power-aware verification.
Preferred: Experience optimizing power in large compute SoCs or multi-die designs.

Benefits

Comp & perks

Medical (including HSA plans)
Dental
Vision
Employee Life & AD&D
401(k)