Principal Micro-architect, Coherent Interconnect

Samsung Electronics

. Lead microarchitecture development of custom coherent interconnect IP and/or last-level cache (LLC) blocks for next-generation designs .

Posted 10/12/2026full-timeUnited StatesLead💰 $221,700 - $364,800 per yearWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates extensive expertise in RTL design and microarchitecture development for coherent interconnect IP and last-level cache blocks, with a strong focus on performance, power optimization, and collaboration across teams. Proven ability to lead technical initiatives and mentor engineers while ensuring functional correctness and robust validation.

Highest-signal resume keywords

RTL DesignCoherent Interconnect ProtocolsVerilog/SystemVerilogMemory Subsystem ArchitectureTechnical Leadership

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

Microarchitecture DevelopmentPerformance OptimizationPower OptimizationLogic DebugTiming ClosureASIC Design FlowSTADFTECO FlowsCoherent Cache Design

Soft Skills

Communication SkillsInterpersonal SkillsMentoring

Tools & Technologies

PerlPython

Industry Keywords

Coherent InterconnectLast-Level CacheOn-Chip Network TopologiesArm AMBA5 CHIAMBA4 ACEAXISnoop Filter Protocols

Tech Stack

Tools & technologies

PerlPython

About the role

Key responsibilities & impact

Lead microarchitecture development of custom coherent interconnect IP and/or last-level cache (LLC) blocks for next-generation designs
Drive coherent interconnect RTL design, including performance and power optimization, logic debug, and timing closure
Own development and delivery of custom coherent interconnect IP and/or LLC blocks
Collaborate with system architects to define and develop coherent interconnect and LLC architectures
Drive microarchitecture definition and specification from architectural exploration and microarchitectural research through detailed specification refinement
Partner with verification teams to ensure functional correctness and robust validation
Develop RTL implementations meeting performance, power, and area (PPA) goals
Work with performance and power teams to optimize architecture and RTL implementations
Collaborate with physical design and CAD teams to resolve implementation, timing, and integration challenges
Provide technical leadership and mentorship to junior engineers

Requirements

What you’ll need

15+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 13+ years of experience with a Master’s degree, or 11+ years of experience with a PhD
Strong background driving RTL design of coherent interconnect and LLC sub-blocks for high-performance digital designs
Demonstrated experience spanning architecture definition through RTL implementation
Familiarity with on-chip network topologies such as mesh, ring, and crossbar interconnects
Working knowledge of Arm AMBA5 CHI, AMBA4 ACE, AXI, and related coherent interconnect protocols
Deep expertise in Verilog/SystemVerilog
Solid understanding of the complete ASIC design flow including STA, DFT, ECO flows, etc.
Strong understanding of memory subsystem architecture, coherent cache design, system caches, coherency mechanisms, and directory-based snoop filter protocols
Proven experience leading technical initiatives, mentoring engineers, and collaborating effectively across dynamic, geographically distributed teams
Strong communication and interpersonal skills
Experience with a scripting language like Perl or Python is a plus
Applicants must be authorized to access U.S. export-controlled information or eligible for government authorization

Benefits

Comp & perks

Medical insurance
Dental insurance
Vision insurance
Life insurance
401(k)
Free onsite lunch
Employee purchase program
Tuition assistance (after 6 months)
Paid time off
Wellness incentives
MBO bonus compensation based on company, division, and individual performance
Long term incentive plan eligibility
Relocation eligibility