Principal RTL Designer – SoC, AI, HPC, Networking

TYLsemi

. Design and implement high-quality RTL for complex SoC components and subsystems .

Posted 9/19/2026full-timeBengaluru • IndiaLeadWebsite

Core Competencies

Role fit

Core Competencies

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Demonstrates extensive expertise in RTL design and micro-architecture, with a strong focus on high-performance and low-power design techniques. Proficient in integrating high-speed IO protocols and optimizing designs for power efficiency and area.

Highest-signal resume keywords

RTL DesignVerilog/SystemVerilogHigh-Speed IO ProtocolsMicro-Architecture DefinitionDebugging and Problem-Solving

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills

RTL DesignMicro-ArchitectureVerilogSystemVerilogHigh-Performance Design TechniquesLow-Power Design TechniquesUCIe ProtocolPCIe ProtocolEthernet ProtocolMemory Interfaces

Soft Skills

CollaborationProblem-SolvingCommunication

Tools & Technologies

Automation ToolsAI ToolsEmulationFPGA PrototypingPythonTcl Scripting

Certifications & Qualifications

Bachelor’s Degree in Electrical EngineeringMaster’s Degree in Electrical Engineering

Industry Keywords

SoC DesignAIHPCNetworkingCoherency ProtocolsInterconnect FabricsSynthesisSTAPhysical Design Constraints

Tech Stack

Tools & technologies

Python

About the role

Key responsibilities & impact

Design and implement high-quality RTL for complex SoC components and subsystems
Own micro-architecture definition and execution for performance-critical blocks
Develop designs that scale across IP, subsystem, and full SoC integration
Integrate and optimize PCIe, CXL, Ethernet, and UCIe high-speed IO protocols
Ensure timing closure, power efficiency, and area optimization
Collaborate with architecture, design verification, physical design, and firmware teams
Drive lint, CDC, RDC, and formal verification quality initiatives
Support emulation, prototyping, and silicon bring-up
Contribute reusable design components and IP across multiple programs
Leverage automation and AI tools to improve RTL productivity and design quality
Deliver high-quality RTL with minimal re-spins and meet performance, power, and area targets

Requirements

What you’ll need

12+ years of relevant experience in RTL design and micro-architecture
Strong expertise in Verilog/SystemVerilog
Strong digital design fundamentals
Experience with high-performance and low-power design techniques
Experience designing for large SoCs in AI, HPC, or Networking domains
Solid understanding of UCIe, PCIe, and Ethernet high-speed IO protocols
Experience with multi-clock, high-bandwidth, and latency-sensitive designs
Strong debugging and problem-solving skills
Bachelor’s/Master’s degree in Electrical Engineering or related field
Experience with memory interfaces such as DDR, HBM, or LPDDR
Familiarity with coherency protocols and interconnect fabrics
Exposure to synthesis, STA, and physical design constraints
Experience with emulation or FPGA prototyping
Working knowledge of Python and Tcl scripting
Ability to work across teams in a fast-paced environment

Benefits

Comp & perks

Remote-friendly work environment
Opportunity to work with a global team
Opportunity to work on consequential AI/HPC semiconductor infrastructure
Work with experienced semiconductor company founders and engineers
Work on products with paying customers, committed capital, LOIs, strategic investors, and a clear path to revenue