Engineer

• Lead signal integrity (SI) and power integrity (PI) analysis and optimization for High-Performance Computing (HPC) using advanced 2.5D/3D packaging technologies
• Partner early in product definition to influence chip floorplanning, power distribution networks, power trees, netlists, and routability tradeoffs
• Evaluate high-speed interface IPs and develop next-generation memory interfaces across IO PHY, SI/PI, and physical design boundaries
• Drive post-silicon validation and qualification for NPI
• Balance SI/PI performance and DFM constraints to achieve final package design closure
• Partner with silicon, system, and external vendor teams
• Develop simulation methodologies to improve modeling accuracy and efficiency
• Collaborate with Chip Design, IP, System Design, software, and vendor teams

Explore Signal and Power Integrity Engineer at SPD Technology. Review requirements and application details.

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