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Posted: 10/15/2026Principal Hardware Engineer – 3rd Party IP Engineer
Marvell TechnologyCore Competencies
Role fitCore Competencies
Use this summary to align your resume positioning with the role.
Demonstrates expertise in managing 3rd party IP integration and compliance within SoC development, with a strong focus on DDR, LPDDR, GDDR, HBM, and eMMC memory interfaces. Proficient in project management and customer engagement to ensure successful core development and validation.
Highest-signal resume keywords
DDR Interface ProficiencySoC PHY Integration UnderstandingProject Management SkillsASIC Design Flow ExposureDesign-For-Test Knowledge
About the role
Key responsibilities & impact- Work as part of Marvell’s Central Engineering 3rd party IP management team
- Bring subcontracted IP under the Marvell IP umbrella
- Integrate DDR, LPDDR, GDDR, HBM, and eMMC memory interface cores
- Define core requirements and validate IP developer competence
- Oversee core development and technology compliance
- Manage core integration, test compliance, and silicon validation across SoC development
- Assist sales in winning bids by working with IP providers to meet customer requirements
- Manage 3rd party developers completing core designs and required design rules
- Advise Marvell design centers on core integration into custom silicon designs
- Hold joint reviews with design centers and 3rd party IP providers
- Develop statements of work and lead provider progress reviews
- Use developer problem-reporting tools to drive issue resolution
- Assist with 8D follow-through for significant supplier issues
Requirements
What you’ll need- Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 10-15 years of related professional experience; OR Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 5-10 years of experience
- Proficient understanding of DDR, LPDDR, GDDR, HBM, and eMMC interfaces
- Understanding of SoC PHY integration, timing analysis, packaging, and multi-chip integrated packaging
- Proficient in project management tasks required to manage 3rd party developers
- Broad-based exposure to ASIC design flows, including logic synthesis, physical design, timing, DRC/LVS, formal verification, and electrical checking
- Understanding of Design-For-Test concepts, including DFT logic insertion, test generation, scan, and embedded core testing
- Good communication and customer management skills
- Limited travel for post-silicon validation at customer sites
- Eligibility to access export-controlled information under U.S. export control laws; non-U.S. persons may be subject to export license review
Benefits
Comp & perks- Bonus and equity plans
- New hire equity grant
- Annual equity refreshers
- Employee stock purchase plan with a 2-year look back
- Family support programs
- Mental health resources
- Recognition and service awards
- Reasonable accommodation during the selection process
ATS Keywords
✓ Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills
DDR InterfacesLPDDR InterfacesGDDR InterfacesHBM InterfacesEMMC InterfacesSoC PHY IntegrationTiming AnalysisLogic SynthesisPhysical DesignDFT Logic Insertion
Soft Skills
Communication SkillsCustomer Management Skills
Tools & Technologies
Problem-Reporting Tools
Industry Keywords
IP ManagementCore DevelopmentSilicon ValidationDesign RulesExport-Controlled Information