Architect jobs in United States
Explore 405 matching jobs.
Memory Architect
Normal Computing
Posted: 10/22/2026PythonC++
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TEKsystems
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Field Service Readiness Architect
Salesforce
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Senior Architect – Chat Platform
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Architect – AWS
Bank of America
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Zscaler
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Stanley Consultants
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Rivian and Volkswagen Group Technologies
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Staff Architect
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Memory Architect
Normal ComputingCore Competencies
Role fitCore Competencies
Use this summary to align your resume positioning with the role.
Demonstrates expertise in memory architecture and circuit design, with a strong focus on high-performance compute and memory systems. Proficient in defining and implementing memory interfaces and architectures while collaborating with cross-functional teams to achieve significant performance improvements.
Highest-signal resume keywords
Memory ArchitectureCircuit DesignPython ProgrammingSPICE ModelingRTL and SystemVerilog
Tech Stack
Tools & technologiesPythonC++
About the role
Key responsibilities & impact- Lead translation of Thermo In-Memory Computing concepts from theory into silicon
- Reimagine memory read/write paths, memory-array organization, and microarchitecture interleaving memory operations with high-performance compute
- Deliver targeted 100–1000× improvements in AI inference performance
- Report to the Director of Silicon Engineering
- Partner with scientists, microarchitects, physical design, and analog design engineers
- Implement a standard cell library combining digital compute primitives with ThermoDRAM compute primitives
- Translate compute primitives into a high-performance Compute In-Memory System
- Own technical relationships with major manufacturers from PDK acquisition through test-chip tapeout and production silicon
- Define processing-in-memory architecture, memory requirements, floorplans, read/write circuitry, and row/column decoders
- Architect local/global datapaths, segmented buses, and on-die fabrics
- Own power distribution, power budgets, thermal limits, redundancy, ECC, retention, and yield considerations
- Own PDK and fab access, design-rule assessment, shuttle tapeout planning, test-chip content, schedule, and bring-up
- Partner with analog engineers on primitive device libraries and set architectural performance requirements
- Define custom memory interfaces including SERDES, PCIe, Ethernet, DDR5, LP6, or HBM-class interfaces
- Oversee SPICE, analytical, and cycle-level performance, power, and yield models
- Partner with performance and machine learning engineers to validate workload-level gains
Requirements
What you’ll need- Substantial experience in memory architecture or circuit design at a memory manufacturer or memory-centric compute company
- Deep understanding of 1T/3T/6T/8T SRAM cells, DRAM bitcells, capacitance, sensing, read/write operations, core timing, retention, and reliability
- Hands-on experience with embedded memory or random access memory technology and PDKs
- Experience developing memory test chips through tapeout
- Fluency moving between SPICE-level circuit behavior and architecture-level performance and power models
- Strong fundamentals in Python, C, C++, or another programming language for modeling and performance prediction
- Experience with RTL and SystemVerilog
- Experience with memory interface types
- Excellent written and spoken communication skills
Benefits
Comp & perks- Equal Opportunity Employer committed to diversity and inclusion
- Reasonable accommodations for individuals with disabilities
- Applicant privacy protections for employment-related personal information
ATS Keywords
✓ Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills
1T/3T/6T/8T SRAM CellsDRAM BitcellsEmbedded Memory TechnologyRandom Access Memory TechnologyMemory Test ChipsPerformance PredictionRead/Write OperationsCore TimingRetentionReliability
Soft Skills
Excellent Communication Skills
Tools & Technologies
SPICEPDKSERDESPCIeEthernetDDR5LP6HBM-class Interfaces
Industry Keywords
Thermo In-Memory ComputingCompute In-Memory SystemMemory RequirementsPower DistributionThermal Limits