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Role fitCore Competencies
Use this summary to align your resume positioning with the role.
Demonstrates expertise in high-speed signaling design, power integrity analysis, and ASIC packaging development. Proficient in using advanced simulation tools and methodologies to ensure optimal performance and reliability in electronic designs.
Highest-signal resume keywords
Signal Integrity AnalysisPower Integrity AnalysisHigh-Speed Design PrinciplesASIC Packaging DevelopmentCadence Sigrity
About the role
Key responsibilities & impact- Develop, document, and implement design rules for ultra-high-speed signaling
- Ensure power, performance, and area goals are met for products
- Analyze substrate signal integrity and power integrity
- Collaborate with layout teams to optimize solutions across interposer, substrate, and PCB
- Design, document, and develop ASIC packages for high-volume, high-quality release
- Perform post-layout extraction and reporting
- Collaborate with system partners, vendors, and design leads
- Resolve complex technical issues using advanced technology design rules
- Help define, design, and verify next-generation ASIC packaging for Cisco platforms
Requirements
What you’ll need- Bachelor’s degree in Electrical Engineering and 4+ years of relevant signal and power integrity experience, or Master’s degree in Electrical Engineering and 2+ years of relevant experience, or PhD in Electrical Engineering and 0+ years of related experience, or equivalent related work experience
- Experience with high-speed design principles, including Transmission Line Theory, electromagnetics, scattering parameters, and impedance network analysis
- Experience applying high-speed design principles to 56G PAM4 SerDes architectures, channel modeling, and BER prediction
- Experience with pre- and post-layout SI/PI simulations using Cadence Sigrity, Ansys HFSS, and Keysight ADS
- Experience conducting layout reviews and physical design validation using Cadence APD and Ansys EM flows
- Experience with SPICE for circuit-level analysis, signal modeling, and performance validation
- Experience articulating technical concepts to diverse audiences, verbally and in writing
- Experience with HBM or high-speed memory interface SI preferred
- Experience with UCIe or proprietary die-to-die interfaces preferred
- Experience with advanced packaging such as CoWoS, EMIB, and interposer-based designs preferred
- Experience with Vector Network Analysis preferred
- Experience with IBIS preferred
Benefits
Comp & perks- Medical, dental and vision insurance
- 401(k) plan with a Cisco matching contribution
- Paid parental leave
- Short- and long-term disability coverage
- Basic life insurance
- Cisco restricted stock unit grants may be available, vesting following continued employment
- 10 paid holidays per full calendar year
- 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday
- Paid year-end holiday shutdown
- 4 paid days off for personal wellness
- 16 days of paid vacation per full calendar year for non-exempt employees
- Flexible vacation time off program with no defined limit for eligible exempt employees
- 80 hours of sick time on hire date and each January 1st thereafter
- Up to 80 hours of unused sick time carried forward annually
- Additional paid time away for critical or emergency family issues
- Optional 10 paid volunteer days per full calendar year
- Annual bonuses may be available for non-sales roles
ATS Keywords
✓ Tailor your resumeApplicant Tracking System Keywords
Tip: use these terms in your resume and cover letter to boost ATS matches.
Hard Skills
Electrical EngineeringTransmission Line TheoryElectromagneticsImpedance Network Analysis56G PAM4 SerDes ArchitecturesChannel ModelingBER PredictionSPICELayout ReviewsPhysical Design Validation
Soft Skills
Technical CommunicationCollaboration
Tools & Technologies
Cadence SigrityAnsys HFSSKeysight ADSCadence APDAnsys EMVector Network AnalysisIBIS
Industry Keywords
High-Speed Memory InterfaceUCIeCoWoSEMIBInterposer-Based Designs