Hardware Engineer

• Develop, document, and implement design rules for ultra-high-speed signaling
• Ensure power, performance, and area goals are met for products
• Analyze substrate signal integrity and power integrity
• Collaborate with layout teams to optimize solutions across interposer, substrate, and PCB
• Design, document, and develop ASIC packages for high-volume, high-quality release
• Perform post-layout extraction and reporting
• Collaborate with system partners, vendors, and design leads
• Achieve combined power and signal integrity
• Resolve complex technical issues using advanced technology design rules

ASIC Packaging Signal/Power Integrity Hardware Engineer

• Lead the full netlist-to-GDSII physical design flow, including floorplanning, power grid design, placement, clock tree synthesis, and place-and-route
• Own static timing analysis, timing constraint creation and validation, and signoff timing closure across operating corners and modes
• Drive physical optimization for power, performance, and area, plus power integrity and crosstalk analysis
• Execute chip/block physical signoff checks, including DRC, LVS, ERC, and antenna fixes, and hand off to the foundry
• Collaborate with RTL, architecture, and DFT teams on floorplanning, macro placement, pin assignments, and physical feasibility
• Create and execute tapeout checklists and manage final stream-out processes
• Support post-silicon physical debugging and bring-up as needed

Hardware Engineer, Physical Design

• Define system and board-level architectures and high-level concepts for new networking products
• Design and develop digital and analog board-level circuits, including high-speed interfaces, clocking, power distribution, and system interconnects
• Apply electrical and signal integrity fundamentals to guide design decisions and resolve high-speed system-level challenges
• Establish and maintain signal integrity rules, design constraints, and compliance requirements
• Specify transceiver SKUs and collaborate with transceiver vendors using optical communications knowledge
• Lead conceptual design, component selection, design simulation, schematic capture, and PCB design-rule development
• Design high-speed buses and perform signal integrity analysis
• Design low-noise, high-efficiency on-board power regulation circuits
• Apply Ethernet standards, including IEEE 802.3, to networking product development
• Support PCB layout, board- and system-level bring-up, debugging, verification, and validation
• Develop and execute hardware validation plans covering functional, performance, interoperability, environmental, and reliability requirements
• Use laboratory and network diagnostic equipment to investigate and resolve hardware issues
• Develop, modify, and support products throughout their lifecycle
• Manage prototype builds and support design transfer, production introduction, and manufacturing readiness
• Support environmental testing, qualification, and release to production
• Investigate development, production, and field failures, identify root causes, and implement corrective actions
• Collaborate with firmware, software, mechanical, systems, validation, manufacturing, supply-chain, vendors, contract manufacturers, and customers
• Drive design reviews, technical tradeoff analyses, documentation, test plans, test procedures, and engineering change processes
• Mentor engineers and provide technical leadership across hardware development projects

Principal Hardware Engineer

• Drive hardware development from concept through mass production
• Own execution through EVT, DVT, and PVT milestones to production launch
• Coordinate firmware, mechanical, supply chain, operations, and other cross-functional teams
• Collaborate with JDM partners on system architecture, requirements, and build schedules
• Lead program reviews, surface risks, remove blockers, and maintain clear timelines
• Participate in design reviews and validation planning
• Coordinate supply chain and operations readiness for manufacturing and deployment
• Troubleshoot schematics, component decisions, and factory build issues
• Travel to Taiwan to collaborate with manufacturing and design teams

• Work with a cross-functional engineering team spanning RF, DSP, firmware, FPGA, software, and test to deliver embedded processing solutions for communications and networking
• Execute and optimize the FPGA firmware implementation lifecycle, from MATLAB/Simulink algorithms and requirements definition through architecture, design, development, implementation, testing, integration, support, and sustainment
• Establish and optimize product development workflows and best practices across the HDL firmware lifecycle, including architecture, design, simulation, verification, and system testing
• Develop microprocessor ICDs between FPGA and message/data handling schemes

Senior FPGA Engineer – RF/Comm Systems/Simulink

• Analyze client needs to develop operational strategies that enhance productivity and business performance
• Collaborate with clients to streamline product development lifecycles and identify bottlenecks
• Implement lean manufacturing principles to optimize supply chain integration and reduce costs
• Leverage digital technologies to improve product quality and speed to market
• Use C#.NET, C++, and Python to develop and maintain software solutions
• Conduct code reviews and adhere to coding standards
• Apply continuous integration and continuous delivery (CI/CD) practices
• Debug and test software to validate functionality and performance
• Design enterprise application architecture and integrate solutions to meet business requirements
• Mentor junior team members and foster a collaborative work environment
• Build client relationships and provide strategic operational solutions

Senior Firmware Engineer

• Define, design, and verify ASICs and ASIC subsystems for Cisco platforms
• Collaborate with a multidisciplinary engineering team to meet power, performance, and area goals
• Design, document, and develop ASIC subsystems for high-volume, high-quality release
• Help define processes, methods, and tools for complex design and implementation
• Collaborate on high-performance ASIC definition and design
• Oversee project code and own, debug, and review complex code
• Document functional and user specifications
• Complete block-level design flow from block specification to tapeout
• Resolve block-level issues
• Write and execute test plans and test benches
• Lead design verification activities and reviews
• Own physical design of multiple blocks or a high-complexity block
• Guide RDL block owners on RTL changes
• Drive signal and power integrity for ASIC integration
• Drive development milestones to successful completion
• Analyze and validate subsystems

ASIC Engineer

• Perform motherboard and system validation testing
• Perform hardware, software, and functional testing using oscilloscopes, logic analyzers, function generators, and other test tools
• Report hardware and software quality issues in bug-tracking systems
• Record and update validation reports for each task performed
• Contribute to validation test plans and test-case preparation
• Research root causes and solutions for discovered quality issues

Hardware Validation Engineer

• Develop block-level and full-chip SDCs
• Work with physical design and DFT teams to close full-chip timing across multiple timing modes
• Understand clocking structures with design and architecture teams
• Develop timing constraints and validate them with constraint verification tools before physical design release
• Identify and resolve timing issues across design levels
• Develop and validate timing constraints using tools such as TCM and Timevision
• Collaborate with front-end and back-end teams to refine design and timing constraints for physical design closure
• Perform optional block-level RTL design or block- or top-level IP integration
• Develop methodologies to promote block-level SDCs to full-chip and push down full-chip SDCs to block level
• Develop and apply methodologies to ensure SDC correctness and quality early in the design cycle
• Review block-level SDCs and clocking diagrams with RTL design owners
• Contribute to full-chip clocking design, diagrams, and documentation
• Contribute to next-generation networking chip development

ASIC Design Hardware Engineer – SDC/STA

• Capture schematics, check layouts, create BOMs, debug, and test server board/add-on card products
• Modify and enhance existing designs to improve server-board quality
• Prepare technical documentation, including product specifications, layout instructions, and test procedures
• Collaborate with cross-functional teams to identify and resolve engineering issues early
• Provide documentation and technical support to contract manufacturers and production during sampling and production
• Support production teams in resolving product problems and customer-related issues
• Perform design verification tests
• Ensure products conform to engineering specifications, regulatory requirements, and customer expectations
• Perform other assigned duties

Hardware Engineer jobs in California

ASIC Packaging Signal/Power Integrity Hardware Engineer

Hardware Engineer, Physical Design

Principal Hardware Engineer