Engineer jobs in United States

Explore 2,359 matching jobs.

Cisco

Senior ASIC RTL Engineer

Cisco

Posted: 10/19/2026
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Arcadis

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Mission Technologies, a division of HII

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Staff Attack Engineer, External

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Senior Attack Engineer, External

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Zero Carbon Systems

Process Modeling Engineer

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Process Optimization Engineer – On-site

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FTI

Preconstruction Engineer

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Posted: 10/19/2026
Verizon

Unified Collaboration Engineer

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BLUE ORIGIN

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Unified Collaboration Engineer

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Cisco

Senior ASIC RTL Engineer

Cisco
Posted 10/19/2026full-timeUnited StatesSenior💰 $167,700 - $245,200 per yearWebsite
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Core Competencies

Role fit
Core Competencies

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Demonstrates expertise in Verilog/SystemVerilog coding and a deep understanding of chip architecture, ensuring high-quality Design for Test (DFT) RTL and robust silicon solutions. Proficient in collaborating with cross-functional teams to align with industry-standard protocols and optimize power performance.

Highest-signal resume keywords
Verilog/SystemVerilog CodingDesign For Test (DFT)Front-End Tools ExperienceIndustry-Standard Interface ProtocolsPost-Silicon Debug

About the role

Key responsibilities & impact
  • Collaborate closely with front-end RTL and backend physical design teams
  • Develop a deep understanding of chip architecture
  • Drive high-quality Design for Test (DFT) RTL
  • Ensure robust and reliable silicon solutions meeting Cisco standards for performance and innovation
  • Contribute to advanced networking silicon aligned with Cisco Silicon One's scalable and flexible architecture

Requirements

What you’ll need
  • Bachelor's or Master's Degree in Electrical or Computer Engineering required
  • At least 7 years of experience
  • Prior experience in Verilog/SystemVerilog coding
  • Prior experience with front-end tools, including Verilog simulators, linting, CDC checkers, synthesis, and formal verification
  • Prior experience with industry-standard interface protocols such as AMBA (AXI, APB, AHB), JTAG, and memories
  • Experience with power optimization techniques, power intent (UPF), and power estimation preferred
  • Prior experience with DFT/MBIST is a plus
  • Prior experience with post-silicon debug preferred

Benefits

Comp & perks
  • Medical, dental and vision insurance
  • 401(k) plan with a Cisco matching contribution
  • Paid parental leave
  • Short- and long-term disability coverage
  • Basic life insurance
  • Cisco restricted stock unit grants may be available, subject to eligibility and continued employment
  • 10 paid holidays per full calendar year
  • 1 floating holiday for non-exempt employees
  • Paid employee birthday day off
  • Paid year-end holiday shutdown
  • 4 paid personal wellness days
  • 16 days of paid vacation per full calendar year for non-exempt employees
  • Flexible vacation time off program with no defined limit for eligible exempt employees
  • 80 hours of sick time off provided on hire date and each January 1st thereafter
  • Up to 80 hours of unused sick time carried forward
  • Additional paid time away for critical or emergency family issues
  • Optional 10 paid volunteer days per full calendar year
  • Annual bonuses for non-sales roles, subject to Cisco policies
  • Performance-based incentive pay for sales-plan employees

ATS Keywords

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Applicant Tracking System Keywords

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Hard Skills
Verilog CodingSystemVerilog CodingDesign For Test (DFT)Power Optimization TechniquesPower Intent (UPF)Power EstimationPost-Silicon DebugFormal VerificationSynthesisLinting
Soft Skills
CollaborationCommunication
Tools & Technologies
Verilog SimulatorsCDC CheckersJTAGAMBA (AXI, APB, AHB)
Certifications & Qualifications
Bachelor's Degree in Electrical EngineeringMaster's Degree in Computer Engineering
Industry Keywords
Chip ArchitectureSilicon SolutionsNetworking SiliconCisco Standards