Engineer jobs in United States
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Senior ASIC RTL Engineer
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Posted: 10/19/2026Project Engineer, Diver
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Posted: 10/19/2026Associate Substation Engineer
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New York University Tisch School of the Arts
Posted: 10/19/2026Industrial Wastewater Process Engineer
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Posted: 10/19/2026Network Firewall Engineer
Booz Allen Hamilton
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CHEP
Posted: 10/19/2026Staff Attack Engineer, External
Horizon3.ai
Posted: 10/19/2026Senior Attack Engineer, External
Horizon3.ai
Posted: 10/19/2026Activation Engineer
Stedi
Posted: 10/19/2026Process Modeling Engineer
Zero Carbon Systems
Posted: 10/19/2026Observability Forward Deployed Engineer
Truist
Posted: 10/19/2026Process Optimization Engineer – On-site
Truist
Posted: 10/19/2026Preconstruction Engineer
FTI
Posted: 10/19/2026Unified Collaboration Engineer
Verizon
Posted: 10/19/2026Tier II Engineer
On Call Compliance Solutions
Posted: 10/19/2026Senior Commodity Engineer – Raw Materials
BLUE ORIGIN
Posted: 10/19/2026Unified Collaboration Engineer
Verizon
Posted: 10/19/2026Core Competencies
Role fitUse this summary to align your resume positioning with the role.
Demonstrates expertise in Verilog/SystemVerilog coding and a deep understanding of chip architecture, ensuring high-quality Design for Test (DFT) RTL and robust silicon solutions. Proficient in collaborating with cross-functional teams to align with industry-standard protocols and optimize power performance.
About the role
Key responsibilities & impact- Collaborate closely with front-end RTL and backend physical design teams
- Develop a deep understanding of chip architecture
- Drive high-quality Design for Test (DFT) RTL
- Ensure robust and reliable silicon solutions meeting Cisco standards for performance and innovation
- Contribute to advanced networking silicon aligned with Cisco Silicon One's scalable and flexible architecture
Requirements
What you’ll need- Bachelor's or Master's Degree in Electrical or Computer Engineering required
- At least 7 years of experience
- Prior experience in Verilog/SystemVerilog coding
- Prior experience with front-end tools, including Verilog simulators, linting, CDC checkers, synthesis, and formal verification
- Prior experience with industry-standard interface protocols such as AMBA (AXI, APB, AHB), JTAG, and memories
- Experience with power optimization techniques, power intent (UPF), and power estimation preferred
- Prior experience with DFT/MBIST is a plus
- Prior experience with post-silicon debug preferred
Benefits
Comp & perks- Medical, dental and vision insurance
- 401(k) plan with a Cisco matching contribution
- Paid parental leave
- Short- and long-term disability coverage
- Basic life insurance
- Cisco restricted stock unit grants may be available, subject to eligibility and continued employment
- 10 paid holidays per full calendar year
- 1 floating holiday for non-exempt employees
- Paid employee birthday day off
- Paid year-end holiday shutdown
- 4 paid personal wellness days
- 16 days of paid vacation per full calendar year for non-exempt employees
- Flexible vacation time off program with no defined limit for eligible exempt employees
- 80 hours of sick time off provided on hire date and each January 1st thereafter
- Up to 80 hours of unused sick time carried forward
- Additional paid time away for critical or emergency family issues
- Optional 10 paid volunteer days per full calendar year
- Annual bonuses for non-sales roles, subject to Cisco policies
- Performance-based incentive pay for sales-plan employees
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